AndrewM | Expert Technical Consulting

Tektronix

Sector Technical Manager

"I have noticed how quickly you have assimilated the technical information needed to understand the CAE marketplace [...] You have demonstrated the ability to work in an unstructured environment with minimal supervision. Your open communications with marketing, engineering, and management have been appreciated, particularly since your observations and concerns were voiced in a positive, productive manner." Click for full text (PDF).
- National Sales Manager, Tektronix CAE Systems Division

Tektronix Logic Analyzer Division


Training Seminars

10 to 15 Engineers (HW designers0 - 1 to 2 day classes

Sales Presentations

  • Custom Applications (Test sets, ATE. up development)
  • Answer any technical questions/ concerns.

Customer support

  • “How can I get this logic analyzer to do xxx?” PS: Salesmen promised it would.
  • Time constraints necessitated over-the-phone solutions
  • Emphasis on patience, tact, speed and successful solutions

Developed Custom Applications SW

  • ATE environment (upload/ download & control software from various hosts)

Tektronix Microprocessor Development Systems


Training Seminars

5 to 10 Engineers (HW and SW designers) - 3 to 5 day classes

Sales Presentations

  • High Speed emulation (12.5 MHz 68000, etc.)
  • Specialized debug environments (ex:: HAC)
  • Answered technical questions

Customer Support

  • For both Hardware and Software
  • Complex “Why does emulator do xxx?” ex: 68000 DMA problem

Custom HW and SW

  • HW modifications to emulators Ex: 9989, 68k (ex: 9989, 6800 DMA)
  • SW (ex: awk translator)

Numerous Hosts

  • Vax VMS
  • Vax and Tek 8560 Unix
  • Tek Dos 2.x

Supported 37 Different Microprocessors

  • Most Popular: 68k, 8086
  • Also: 6800, Z80, Z8000

Target Software Support

  • Assembly level languages
  • Unix based system, “C”, Pascal

Tektronix Logic Design System

Trained on Daisy, Valid, Futurenet, IBM CBDS
Provided Competitive Analysis
Daisy Videotape - Valid Logic Training
Phoenix Data Sys - Silvar Lisco
Performed Chip Model Development
Acted as Interface between marketing and engineering
Gate Array Design
Universal Semiconductor
1200 gates on 1500 array
Library Research
Market Research
Account Analysis: Rockwell International

Travel

Albuquerque - Beaverton
Portland - San Francisco
Sunnyvale - Austin